1. Field of the Invention
This invention relates to a memory device that selectively accepts accesses using a serial interface and accesses using a parallel interface.
2. Description of the Related Art
A memory device, such as a flash memory, uses an architecture that is capable of accepting access using a simple four-wire serial interface. The memory device using a serial interface is usually incorporated into an 8-pin or 16-pin chip package, for example, as shown in FIG. 6. Therefore, compared with a memory device using a parallel interface, the serial interface equipped memory device can be easily downsized and accordingly the cost of the chip package can be reduced.
For example, when an 8-pin chip package is used, four of the eight pins are allocated to terminals of a four-wire serial interface, i.e. an address/data input terminal (SI), a data output terminal (SO), a chip select terminal (CS#), and a system clock input terminal (SCK), while 2 pins are allocated to power source terminals (VDD and VSS). The remaining pins, i.e. two pins, are allocated to control terminals, such as a write protect terminal that determines allowance when an access for writing/erasing is received, a reset terminal that stops processing in response to an interrupt request, or a hold terminal that interrupts the processing and holds the condition.
FIG. 7 shows a memory device 100 equipped with a serial interface that includes an address buffer/latch section 10, a control logic section 12, a data register 14, an X decoder 16, a Y decoder 18, a memory array 20, a serial-parallel conversion section 22, and a parallel-serial conversion section 24.
FIG. 8 is a timing diagram showing the control processing for reading data out of the memory device 100.
First, the electrical potential of the chip select terminal (CS#) is changed to a low level to select the memory device 100 as an object to be accessed. In response to the potential change of the chip select terminal (CS#) to the low level, the control logic section 12 brings other sections into a command receivable state.
Next, a data reading command (i.e. 03h shown in FIG. 8), that instructs reading of data, is input from the address/data input terminal (SI). The command is arranged, for example, as 8-bit data and is serially input to the serial-parallel conversion section 22, bit by bit, in synchronism with a system clock input from the system clock input terminal (SCK). The serial-parallel conversion section 22 converts the command from the serial data into parallel data corresponding to a bit width of an internal bus (e.g. 8 bits). The converted parallel data is sent to the control logic section 12.
The control logic section 12 analyzes the command. For example, when the input command is a data reading command (03h), the control logic section 12 brings other sections into an address value receivable state.
Next, an address value (Add.) is input from the address/data input terminal (SI). The address value is, for example, expressed as 24-bit serial data and is input to the serial-parallel conversion section 22, bit by bit, in synchronism with the system clock. The serial-parallel conversion section 22 successively converts the address value from the serial data into parallel data corresponding to the bit width of the internal bus (e.g. 8 bits). The control logic section 12 causes the serial-parallel conversion section 22 to successively transfer the address value, being converted into the parallel data, to the address buffer/latch section 10.
The address buffer/latch section 10, when the address value has been received, outputs a control signal to each of the X decoder 16 and the Y decoder 18 to identify a corresponding memory element in the memory array 20, and the data stored in this memory element is read out. The readout data is stored, via the Y decoder 18, into the data register 14. The parallel-serial conversion section 24 converts the data stored in the data register 14 into serial data and outputs the converted serial data from the data output terminal (SO) in synchronism with the system clock.
The address buffer/latch section 10 successively increases the address value so that the memory array 20 can successively read the data out of a memory element identified by the next address value.
However, according to such a memory device using a four-wire serial interface, the input/output of address value and data is performed by 1-bit serial communication, and accordingly the transfer rate is very low compared with that of the memory device using a parallel interface.